Embodiments of the present invention provide a hybrid analog-to-digital converter, which may be employed in image sensors for digital still cameras or digital video cameras. Further embodiments of the present invention provide an image sensor, which may be employed in digital still cameras or digital video cameras. Further embodiments of the present invention provide a method for providing a plurality of digital signals based on a plurality of analog input signals.
Different approaches exist for the conversion of a plurality of analog-to-digital channels (for example, several thousands). Due to the high number of converters necessitated, the parameters power and area have significant borders, limiting a maximum number of converters, and therefore a maximum number of channels that can be converted simultaneously. Analog-to-digital converters (ADCs) for converting a high number of channels are especially used in image sensors.
In image sensors the power and area requirements for analog to digital converters set significant limitations for resolution and frame rate.
CMOS (Complementary-Metal-Oxide-Semiconductor) image sensors necessitate very power and area effective analog-to-digital converters due to very high column count and small column spacing. CMOS image sensors have substantially improved in recent years. The development is driven by digital still cameras and imagers in mobile devices. Integrating the analog-to-digital converter on the CMOS image sensor is a key feature when building a cost effective camera on chip. The pixel race is still ongoing, which leads to severe design demands for the ADC. In megapixel image sensors several thousand columns (e.g. 4000 and more) with a spacing of 1.5 μm to 10 μm result in tough constrains for the area and power of the ADC.
In conventional image sensors typically column-converters are used for the digitization. These are converters, which are arranged in a column pattern, wherein each converter converts analog signals from photo detectors in its column. A column pattern (or column spacing) of typical image sensors is in the range between 1.5 μm to 10 μm. The number of columns may, for example, be 4000. Due to the number of columns, the available power per converter is limited. As a result, a warming of the image sensor, which leads to an increase in the dark current of the photodiodes (or in general of the photo detectors) of the image sensor, which is not tolerated. Otherwise may the increase in dark current lead to a decrease in image quality. As it can be seen, a problem with image sensors is the parallel digitization of a high number of channels with a very limited area and power.
Recently ADCs on imagers have moved from imager level (where typically pipeline ADCs have been used) to column level (where often slope converters are used).
For more details on image level ADCs see Centen, P.; Lehr, S.; Neiss, V.; Roth, S.; Rotte, J.; Schemmann, H.; Schreiber, M.; Vogel, P.; Boon-Keng Teng; Damstra, K.; “A ⅔ inch CMOS Image Sensor for HDTV Applications with Multiple High-DR Modes and Flexible Scanning,” Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, pp. 512-619, 11-15 Feb. 2007.
For more information on column level ADCs see also Woodward Yang; Oh-Bong Kwon; Ju-Il Lee; Gyu-Tae Hwang; SukJoong Lee; “An integrated 800×600 t-MOS imaging system,” Solid State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 JEEE International, vol., no., pp. 304-305, 1999 doi: 10.1 109/ISSCC.1999.759261.
FIG. 8 shows a block diagram of a column level analog-to-digital converter within an image sensor. In this architecture, the analog-to-digital converter is directly at the column of the pixel array of an image sensor. There is thus no need for horizontal multiplexing. The main drawback of this architecture is the limited space and power. Today's trends towards smaller pixels lead to column spacing of a few μm (down to 1.5 μm). Although column pitch can be usually doubled by dividing the ADC to top and bottom of the imager (as it is shown in FIG. 8), however, it is still very small for integrating an analog-to-digital converter for each column. Not many analog-to-digital converter architectures are easily integratable in this space.
A popular approach is a single slope implementation, but this architecture is not feasible for increasing pixel counts and ADC resolution as the time for the comparator is reduced by both (by the increasing pixel counts and the increasing ADC resolution). In conventional image sensors, these slope converters are used very frequently, but, as mentioned, this approach is not applicable for larger image sensors (comprising several megapixels) and with higher resolutions (equal to or above 12 bits), because of the necessitated time for the comparator decisions becoming too low.
Recently a multi-ramp approach has been reported (see also Snoeij, M. R.; Donegan, P.; Theuwissen, A. J. P.; Makinwa, K. A. A.; Huijsing, J. H.; “A CMOS Image Sensor with a Column-Level Multiple-Ramp Single-Slope ADC,” Solid-Stare Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International pp. 506-618, 11-15 Feb. 2007).
According to Xiang fang, Srinvasan, V., Wills, J., Granacki, J., LaCoss, J., Choma J., “CMOS 12 bits 50 kS/s micropower SAR and dual-slope hybrid ADC,” Circuits and Systems 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on, vol., no., pp. 180-183, 2-5 Aug. 2009 doi: 10.1109/MWSCAS.2009.5236122, a combination of a successive approximation ADC (SAR-ADC) and dual slope ADC is shown. This converter has a successive approximation stage and a dual slope integrator stage. The converter shown in this document is not applicable for image sensors, due to the area it necessitates, because it would necessitate an implementation of the dual slope integrator and a successive approximation stage for every converter, and therefore, for every column of the image sensor.